1. Field of the Invention
The present invention relates generally to post-process wafer evaluation. More specifically, the present invention relates to a system for enabling graphical presentation and control of a post-process wafer evaluation.
2. Description of the Related Art
Semiconductor wafers undergo numerous processes during the semiconductor manufacturing process. Layers may be added, patterned, etched, removed, and polished, among others. After each process the wafer is typically examined to confirm the previous process was completed with an acceptable level of post-process error or nonuniformity. The various operating variables (e.g., event timing, gas pressure, concentrations, temperatures, etc. . . . ) of each process performed on the wafer are recorded so that any changes in any variable may be quickly identified and potentially correlated to any post-process error or nonuniformity discovered when the wafer is examined.
Prior art approaches to describing post-process nonuniformities include subjective, verbal descriptions such as “center-fast” for annular nonuniformity or “left-side-slow” for azimuthal nonuniformity. Center-fast is generally descriptive of a post-process wafer condition where more material has been removed from a center region on the wafer than from a surrounding region on the wafer. However, center-fast does not provide a specific, objective, and quantitative description of the nonuniformity. Similarly, left-side-slow is generally descriptive of a post-process wafer condition where less material has been removed from a left side region on the wafer than from a remaining region on the wafer. As with the center-fast description, the left-side-slow description fails to provide a specific, objective, and quantitative description of the nonuniformity.
Descriptions of post-process nonuniformities are used to provide feedback to correct errors and inconsistencies in the preceding wafer processes. Descriptions of post-process nonuniformities can also be used to track the impact of the nonuniformities on subsequent semiconductor manufacturing processes and on metrics from completed semiconductor devices (e.g., device yields, performance parameters, etc. . . . ).
As post-process nonuniformities become smaller and smaller, the post-process nonuniformities become less symmetrical and more difficult to accurately describe with the subjective, verbal descriptions. In following, the subjective, verbal descriptions are insufficient to accurately describe the post-process nonuniformities so that further improvements in the preceding wafer processing operations can be successfully implemented.
In view of the foregoing, there is a need for a system that enables a detailed graphical display and analysis of a post-process wafer condition.